I am the inventor (or co-inventor) of the inventions described in the following patents and patent publications:

US 5,982,317 : Oversampled Digital-to-Analog Converter Based on Nonlinear Separation and Linear Recombination

This patent teaches how to implement a mismatch-shaping encoder for use with an array of scaled (say, binary weighted) analog sources, such as to implement a high-resolution digital-analog converter. The invention is useful, in part, to implement the data converters needed for audio CD and DVD playback units.

US 6,215,348 : Bootstrapped Low-Voltage Switch

This patent teaches how to implement CMOS switches that has a nearly signal-independent impedance.  They can be used to implement the sampling switch in high-speed data converters.  They can operate from a supply voltage that is only marginally higher than the technology's threshold voltage, and hence these switches are also use for the implementation of general-purpose low-voltage switched-capacitor circuits.

US 6,271,782 : Delta-Sigma A/D Converter

This patent teaches how to implement a specific hybrid of delta-sigma A/D converters.  It also teaches a system topology that is now widely used to stabilize delta-sigma data converters based on a continuous-time loop filter.

US 6,348,884 : Idle-tone-Free Mismatch-Shaping Encoders

One may show that first-order mismatch-shaping generally is sufficient to suppress the errors introduced by element mismatch in data converters implemented in a typical CMOS technology (the matching is pretty good, and kT/C noise will generally dominate the mismatch-induced noise even at relative low oversampling ratios).  Idle tones, however, are a real problem in most first-order mismatch-shaping encoders.  Second-order encoder are generally much better in terms of idle tones, but their complexity is prohibitive.  This patent teaches how to eliminate idle tones in even the simplest first-order mismatch-shaping encoders, which effectively voids the need for higher-order encoders.

US 6,473,011 : Serial D/A Converter Compensating for Capacitor Mismatch Errors

This patent teaches how a high-performance D/A converter can be implemented using only two capacitors and a small digital state machine. The technique is remarkable in its simplicity, but it does not measure up to other techniques in terms of performance versus power consumption.

 US 6,556,158 : Residue-Compensating A/D Converter

This patent teaches how the best properties of pipeline ADCs (high throughput, low circuit complexity) can be combined with the best properties of delta-sigma ADCs (low sensitivity to mismatch and other circuit imperfections).  The result is a high-throughput (>10MS/S) and high-resolution (14-16 bits) data converter with relatively low circuit complexity and power consumption.

US 6,573,790 : Wide-Bandwidth Operational Amplifier

This patent teaches how the principles that have been applied very successfully to delta-sigma data converters can be re-used with significant advantage for the implementation of low-distortion amplifiers.  A main limitation for this invention is that it requires that the amplifier's load is well controlled.

US 6,952,174:  Serial Data Interface

This patent teaches how the data stream from a two-bit delta-sigma ADC can be encoded by a small digital state machine such that it can be communicated over a serial interface.  The encoding is performed such that relatively few transitions occur on the interface, which results in a net power savings, while exhibiting a good robustness to bit errors.